The present invention relates to dynamic relocation of storage and, more particularly, to interlocking operations under dynamic relocation of storage in an address-sliced cache subsystem.
In certain computing systems and architectures, main memory is a primary resource that hypervisors manage on behalf of logical partitions, or guest operating systems. Similar to compute resources, main memory is limited in size and the main memory needs of a logical partition or operating system may change over time. To better utilize the shared memory resources of a computer system, advanced hypervisors and computer systems support dynamic (i.e., while a partition is active) allocation and de-allocation of storage in fixed size increments. The hypervisors are formed of low-level machine code that runs on processors to manage allocations of logical partitions in terms of dispatching logical processors associated with the partitions as well as the allocation of memory to the logical partitions.
While the means to move logical partitions between different physical compute resources exists, main memory cannot be relocated between physical partitions (also referred to as nodes or drawers) for an active logical partition without first disrupting the partition. Typically, a disruption can mean either suspending the partition or the entire system while performing the relocation. Thus, since main memory associated with an active logical partition cannot be moved non-disruptively, optimal resource allocation over time is not obtained and in fact memory resource allocation may become suboptimal over time as compute and memory resource demands change.
In shared cache designs which support high number of operations from a large number of processors, caches are often sliced by some system address index bits to maintain adequate throughput. These address-based cache slices, or cache pipes, are usually assigned on consecutive cache line addresses and perform cache-related operations autonomously as coherency management across the caches and memory can be performed on the cache line size basis.
Certain systems feature storage access protection keys to limit the access scope of a main program or user from beyond its assigned storage address space. The operation system within the logical partition manages the allocation and de-allocation of the pages across the programs or users in its partition, clearing and assigning a new key each time a page is de-allocated and allocated. In addition, the page change status bit is associated with the access protection key so as to indicate if a paging action between system and I/O storage is needed on a page de-allocation.
In certain systems, when a processor accesses a unit of data from storage, it is returned 2 pieces of information: a 256 bytes of storage data (cache line) where the requested unit of data is located, and a key value associated with the page in which the cache line was fetched from. The returned key is then checked against the key assigned to the program or user to determine if the access is in violation or is permitted before continuing with program execution. With systems supporting up to multiple terabytes of system memory, the amount of keys needed can be up to gigabytes of capacity, beyond the capacity of the processor caches. Therefore in certain systems, it is appropriate to have the keys physically located in a reserved region of the system memory where the page data resides and is accessed in conjunction with the data.